Job: IRC100331
Job Title : Software Engineer
Location : India
Organization Name : FPGA SW
Detailed Description:
The candidate will have an opportunity to work on the latest Xilinx tools and also interact with the customers for timing closure and design feedback.
Responsibilities:
1. Help give feedback to synthesis & implementation tools based on customer designs and its analysis.
2. Interact with customers and guide in helping them achieve timing closure and routability using design changes & software.
3. Create and maintain methodology to measure Quality of Results and the design suite associated with it.
Job Requirements :
1. Masters in relevant area and 1+ years relevant experience
2. Familiarity with VHDL, Verilog and Implementation tools including synthesis, place and route
3. Timing Closure
4. Knowledge of EDA algorithms is an added bonus
Additional Details :
Applicants are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status or sexual orientation. The information requested here is not gathered for employment decisions. It is used only for compliance with Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.
Currency : INR
Vacancy Type : Employee
APPLY NOW
Job Title : Software Engineer
Location : India
Organization Name : FPGA SW
Detailed Description:
The candidate will have an opportunity to work on the latest Xilinx tools and also interact with the customers for timing closure and design feedback.
Responsibilities:
1. Help give feedback to synthesis & implementation tools based on customer designs and its analysis.
2. Interact with customers and guide in helping them achieve timing closure and routability using design changes & software.
3. Create and maintain methodology to measure Quality of Results and the design suite associated with it.
Job Requirements :
1. Masters in relevant area and 1+ years relevant experience
2. Familiarity with VHDL, Verilog and Implementation tools including synthesis, place and route
3. Timing Closure
4. Knowledge of EDA algorithms is an added bonus
Additional Details :
Applicants are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status or sexual orientation. The information requested here is not gathered for employment decisions. It is used only for compliance with Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.
Currency : INR
Vacancy Type : Employee
APPLY NOW
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